Converting information in the form of analog signals to equivalent information in digital form is historic and ubiquitous in the microelectronics industry. This is because a great deal of the information produced by the physical world is analog in nature, e.g., audio signals, video signals, magnetic and electric fields, etc. As the ability to process information in digital form increases exponentially with the sophistication and scaling of digital integrated circuits, there is an ever increasing desire to convert analog signals to digital form to take advantage of these increased digital processing capabilities.
There are several approaches to the task of converting analog signals to digital form. These include various architectures or algorithms that can be implemented using analog and digital circuit designs. These architectures include flash analog-to-digital converters (ADCs), delta-sigma ADCs, pipelined ADCs, and several others. Two notable specifications of interest in an ADC are the sampling rate and the nominal resolution. The sampling rate is the rate in samples per second (s/S) at which the analog input is converted to a digital output. The nominal resolution is the number of bits in the digital output and is related to the accuracy with which the digital output represents the analog input. For example, in a one-bit ADC, the only property of the input that can be expressed in the output is whether or not it is above or below some level; in a two bit converter the input can be expressed as being in one of four regions, etc. As the number of bits of precision is increased, the accuracy with which the digital output approximates the true analog input improves but the error never goes to zero. This so-called quantization error is an inherent impairment of analog-to-digital converters.
One approach to analog-to-digital conversion is called successive approximation. In this approach, as with all ADCs, the analog input is constrained to fall within some predetermined range called the full-scale range. In a successive approximation converter, a digital-to-analog converter (DAC) whose output is constrained to nominally the same full-scale range is present. In a first processing step, the analog signal is sampled and held for subsequent conversion steps. In a second conversion step, a comparator circuit compares the sampled analog input to the DAC output when the DAC input is set to exactly one-half of its full-scale digital range. By this method, the analog input is determined to be in either the bottom half of the full-scale range (e.g., when the comparator output reads binary zero) or in the top half of the range (e.g., when the comparator reads a binary one). The result of this decision is the most significant bit (MSB) of the ADC's digital output. In a third conversion step, the DAC input is re-set to a value halfway between its half full scale value and either the zero value or the maximum value depending on the result of the comparison in the second step. By this method, the analog input is determined to be in either the bottom half or the top half of the remaining possible range of values after the result of the comparison in the first step. In subsequent conversion steps, this process is repeated until all bits in the ADC digital output are decided.
The successive approximation converter provides analog simplicity and ease of implementation in digital-centric CMOS integrated circuit fabrication processes. Such a converter requires at least ‘N’ steps to complete its task, where ‘N’ is the number of bits in the digital output. Typically at least one additional step is added to allow for sampling and/or settling at the analog input. A number ‘m’ of additional steps may be added for other purposes, bringing the total number of steps to N+1+m. Each step in the conversion process is typically allotted a fixed time ‘T’ associated with the period of a clock available on the chip/system in which the ADC operates. As a result the time required for each conversion is Tconv=(N+1+m)*T seconds where the converter sample rate is limited to 1/Tconv samples per second (s/S).
Another approach to analog-to-digital conversion is time interleaving. In this approach, a plurality of identical converter unit cells operate on an analog signal sampled at a multiple of the sample rate of each converter where the multiple is equal to the number of converter unit cells in the plurality of converter unit cells. For an analog signal sampled at time interval T seconds, e.g., having a sample rate of 1/T samples/second (s/S), two converters each operating at a sample rate of ½T s/S can be used to digitize these samples at an aggregate rate of 1/T s/S. A first analog sample is sent to the first of the two converters at time zero and a second analog sample is sent to the second converter at time T. The first converter completes its task at time 2T at which time a third analog sample is sent; the second converter completes its task at time 3T and a fourth analog sample is sent; and the process repeats. Similarly, three identical converters operating at a sample rate ⅓T can achieve the same result, and so on. Each additional cycle required by the individual converter can be accommodated at the same system sample rate by adding another converter to the plurality of converters in the time interleaved system. In this manner a plurality of N slow converters can be operated in such a way as to achieve an effective sample rate of N times the sample rate of the slow converters.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.